[{"data":1,"prerenderedAt":107},["ShallowReactive",2],{"GET-live-training-course/slug/intel-processor-and-platform-architecture-{}-{}":3},{"data":4},{"id":5,"name":6,"slug":7,"description":8,"about":9,"training_materials":10,"you_will_learn":11,"prerequisites":12,"is_active":13,"category_id":14,"duration":15,"modified_at":16,"course_outline":17,"supplied_materials":16,"thumbnail":18,"elearning_courses":19,"ebooks":47,"topics":78,"reviews":103,"meta_title":16,"meta_description":16,"meta_keywords":16},699,"Intel Processor and Platform Architecture","intel-processor-and-platform-architecture","\u003Cp class=\"MsoNormal\" style=\"margin-bottom: .0001pt; line-height: normal;\">Each CPU and chipset generation brings new capabilities while maintaining backward compatibility with earlier platforms. New 9th and 10th generation CPU architectures offer significant improvements in instruction throughput, power conservation, integrated graphics, security, system-on-a-chip (SOC) packaging options, etc. This 5-day course introduces the x86 Instruction Set Architecture (ISA) and describes the hardware features of the latest Intel Core and Xeon CPUs supporting it. In addition, the course presents an overview of memory, platform controller hub (PCH) logic, and IO interfaces that may be employed when implementing common system types.\u003C/p>\r\n\u003Cp class=\"MsoNormal\" style=\"margin-bottom: .0001pt; line-height: normal;\"> \u003C/p>\r\n\u003Cp class=\"MsoNormal\" style=\"margin-bottom: .0001pt; line-height: normal;\">\u003Cspan style=\"color: rgb(186, 55, 42);\">\u003Cstrong>All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.\u003C/strong>\u003C/span>\u003C/p>","\u003Cp class=\"sectionsubhead\">\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"Intel Processor and Platform Architecture\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cul>\r\n\u003Cli>PDF of course slides\u003C/li>\r\n\u003Cli>\"\u003Ca href=\"../../ebook/x86-instruction-set-architecture\">x86 Instruction Set Architecture\u003C/a>\" eBook\u003C/li>\r\n\u003Cli>Optional Add-On: \u003Ca href=\"../../elearning-course/intel-x86-processor-and-platform-architecture-elearning-course\">Intel Processor and Platform eLearning\u003C/a> course\u003C/li>\r\n\u003C/ul>","\u003Cul>\r\n\u003Cli>Intel x86 CPU and Chipset Evolution\u003C/li>\r\n\u003Cli>Current Core and Xeon CPUs: Ice Lake, Cascade Lake, plus “Refresh” Variants\u003C/li>\r\n\u003Cli>x86 Instruction Set Architecture (ISA) and CPU Operating Modes\u003C/li>\r\n\u003Cli>Core and Xeon CPU Microarchitecture Differences\u003C/li>\r\n\u003Cli>Caches\u003C/li>\r\n\u003Cli>Platform Addressing\u003C/li>\r\n\u003Cli>Main Memory DRAM\u003C/li>\r\n\u003Cli>Ultra Path Interconnect (UPI)\u003C/li>\r\n\u003Cli>CPU Integrated Graphics\u003C/li>\r\n\u003Cli>CPU Integrated IO (IIO)\u003C/li>\r\n\u003Cli>Interrupt Handling\u003C/li>\r\n\u003Cli>Hardware Virtualization Support\u003C/li>\r\n\u003Cli>Platform Controller Hub (PCH) Features\u003C/li>\r\n\u003Cli>Power and Thermal Management\u003C/li>\r\n\u003Cli>CPU Performance Monitoring\u003C/li>\r\n\u003C/ul>","\u003Cp>A basic understanding of computer architecture is helpful.\u003C/p>",true,8,"5 days",null,"\u003Cul>\r\n                \u003Cli>Intel x86 Core and Xeon Platform Background\r\n                \u003Cul>\r\n                    \u003Cli>Intel 64 and IA-32 CPU lineage\r\n                    \u003Cul>\r\n                        \u003Cli>80386 to Ice Lake/Cascade Lake\u003C/li>\r\n                        \u003Cli>Core and Xeon CPUs Expected Next\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Ice Lake/Cascade Lake Platform Examples\r\n                    \u003Cul>\r\n                        \u003Cli>Gaming Desktop\u003C/li>\r\n                        \u003Cli> 2-in-1 Laptop\u003C/li>\r\n                        \u003Cli>Xeon Scalable CPU Server\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>x86 Instruction Set Architecture (ISA)\r\n                \u003Cul>\r\n                    \u003Cli>CPU Core Fetch/Decode/Execute Role\u003C/li>\r\n                    \u003Cli>x86 Instruction Basics\u003C/li>\r\n                    \u003Cli>Instruction Set Overview\r\n                    \u003Cul>\r\n                        \u003Cli>General Purpose Instructions\u003C/li>\r\n                        \u003Cli>Floating Point and SIMD Instructions\u003C/li>\r\n                        \u003Cli>Program Flow Instructions\u003C/li>\r\n                        \u003Cli>Hardware-Related Instructions\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>x86 Register Set Overview\r\n                    \u003Cul>\r\n                        \u003Cli>General Purpose Registers (GPRs)\u003C/li>\r\n                        \u003Cli>X87/MMX Registers\u003C/li>\r\n                        \u003Cli>XMM/YMM/ZMM Registers\u003C/li>\r\n                        \u003Cli>Segmentation Registers\u003C/li>\r\n                        \u003Cli>Control Registers\u003C/li>\r\n                        \u003Cli>Debug Registers\u003C/li>\r\n                        \u003Cli>Model-Specific Registers (MSRs)\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>x86 CPU Operating Modes\r\n                    \u003Cul>\r\n                        \u003Cli>Real Mode\u003C/li>\r\n                        \u003Cli>Protected Mode\u003C/li>\r\n                        \u003Cli>Virtual-8086 Mode\u003C/li>\r\n                        \u003Cli>System-Management Mode (SMM)\u003C/li>\r\n                        \u003Cli>IA32e (Long) Mode\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Platform Addressing\r\n                \u003Cul>\r\n                    \u003Cli>Introduction to x86 Address Spaces\r\n                    \u003Cul>\r\n                        \u003Cli>Memory (DRAM and MMIO Space)\u003C/li>\r\n                        \u003Cli>IO (Fixed and Relocatable Legacy Registers)\u003C/li>\r\n                        \u003Cli>PCI (Peripheral Component Interconnect) Space\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Platform Traffic Types\r\n                    \u003Cul>\r\n                        \u003Cli>Programmed IO (PIO)\u003C/li>\r\n                        \u003Cli>DMA (Direct Memory Access)\u003C/li>\r\n                        \u003Cli>Peer-to-Peer\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Memory Segmentation\u003C/li>\r\n                    \u003Cli>Real Mode\r\n                    \u003Cul>\r\n                        \u003Cli>Protected Mode\u003C/li>\r\n                        \u003Cli>Memory Paging\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Paging\r\n                    \u003Cul>\r\n                        \u003Cli>Translation Lookaside Buffer (TLB) Role\u003C/li>\r\n                        \u003Cli>x86 Paging Modes: Basic 4K Paging, PSE, PAE, IA32e Mode Paging\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Core CPU Microarchitecture (10th Generation Ice Lake)\r\n                \u003Cul>\r\n                    \u003Cli>CPU Internal Architecture Overview\u003C/li>\r\n                    \u003Cli>Processor Instruction Pipeline & Execution Units\u003C/li>\r\n                    \u003Cli>Implications of HyperThreading\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Architectural Differences: Cascade Lake Xeon Scalable CPU vs. Ice Lake Core CPU\r\n                \u003Cul>\r\n                    \u003Cli>Maximum Core/Thread Count = 28/56\u003C/li>\r\n                    \u003Cli>Enhanced AVX Execution Unit Resources\u003C/li>\r\n                    \u003Cli>32KB L1 Code/Data Caches, 1MB L2 Unified Cache\u003C/li>\r\n                    \u003Cli>Non-inclusive L3 Cache with 2D Mesh Interconnect\u003C/li>\r\n                    \u003Cli>L3 Cache Slice Distributed Caching/Home Agent (CHA)\u003C/li>\r\n                    \u003Cli>ECC DRAM and Support for Persistent Memory (Optane) PMDIMMs\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Cache Topics\r\n                \u003Cul>\r\n                    \u003Cli>Cache Basics\r\n                    \u003Cul>\r\n                        \u003Cli>Five Memory Map Region Types: UC, WC, WB, WT, WP\u003C/li>\r\n                        \u003Cli>Cache Policy Management: MTRRs and Paging Structures\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>CPU Conduct in the Five Memory Regions\u003C/li>\r\n                    \u003Cli>Cache Hardware Architecture\u003C/li>\r\n                    \u003Cli>Cache/Memory QoS and Intel Resource Director Technology (RDT)\r\n                    \u003Cul>\r\n                        \u003Cli>Cache Monitoring Technology (CMT)\u003C/li>\r\n                        \u003Cli>Cache Allocation Technology (CAT)\u003C/li>\r\n                        \u003Cli>Code and Data Priority (CDP)\u003C/li>\r\n                        \u003Cli>Memory Bandwidth Monitoring (MBM)\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Other Cache Topics\r\n                    \u003Cul>\r\n                        \u003Cli>PAT Feature\u003C/li>\r\n                        \u003Cli>Software Prefetch Instruction\u003C/li>\r\n                        \u003Cli>Non-Temporal Data\u003C/li>\r\n                        \u003Cli>Data Direct IO (DDIO)\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Key Platform Interfaces\r\n                \u003Cul>\r\n                    \u003Cli>CPU and PCH Interface Overview\u003C/li>\r\n                    \u003Cli>Main Memory DRAM\u003C/li>\r\n                    \u003Cli>Intel Ultra Path Interconnect (UPI)\u003C/li>\r\n                    \u003Cli>PCI Express (PCIe)\u003C/li>\r\n                    \u003Cli>Universal Serial Bus (USB)\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>PCI Configuration Space\r\n                \u003Cul>\r\n                    \u003Cli>Basics of Discovery and Enumeration\u003C/li>\r\n                    \u003Cli>Client and Server Machine PCI Topology Examples\u003C/li>\r\n                    \u003Cli>PCI Headers, Compatible Configuration Space, Extended Configuration Space\u003C/li>\r\n                    \u003Cli>Accessing PCI Configuration Space\u003C/li>\r\n                    \u003Cli>Arbor Software View of PCI Configuration Space\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Platform Interrupt Handling\r\n                \u003Cul>\r\n                    \u003Cli>IOAPIC\u003C/li>\r\n                    \u003Cli>Local APICs\u003C/li>\r\n                    \u003Cli>Message Signaled Interrupt (MSI/MSI-X) Basics\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Platform Power Management\r\n                \u003Cul>\r\n                    \u003Cli>ACPI Overview\u003C/li>\r\n                    \u003Cli>CPU Power Management Features\u003C/li>\r\n                    \u003Cli>PCH Power Management\u003C/li>\r\n                    \u003Cli>IMC and DRAM Power Management\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Platform Thermal Management\r\n                \u003Cul>\r\n                    \u003Cli>CPU Thermal Management Overview\u003C/li>\r\n                    \u003Cli>PCH Thermal Management\u003C/li>\r\n                    \u003Cli>DRAM Thermal Management\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>System Management Mode (SMM)\u003C/li>\r\n                \u003Cli>Machine Check Architecture (MCA)\u003C/li>\r\n                \u003Cli>Other Topics (Coverage Depends on Interest Level and Time Available)\u003C/li>\r\n                \u003Cli>Virtualization Overview\u003C/li>\r\n            \u003C/ul>","https://mindshare-prod.s3.amazonaws.com/public/live_training_courses/thumbnails/live_training_course_699_thumbnail_1748361048.png",[20],{"id":21,"name":22,"slug":23,"description":24,"whats_included":25,"about":26,"instructor_fullname":27,"instructor_email":28,"equivelent_of":29,"subscription_length":30,"price":31,"price_arbor":31,"course_category_id":32,"elearning_courses":33,"you_will_learn":11,"prerequisites":34,"is_active":13,"modified_at":35,"order":36,"modules_count":37,"video":38},1735,"Intel x86 Processor and Platform Architecture eLearning Course","intel-x86-processor-and-platform-architecture-elearning-course","\u003Cp>Each CPU and chipset generation brings new capabilities while maintaining backward compatibility with earlier platforms. New 9th and 10th generation CPU architectures offer significant improvements in instruction throughput, power conservation, integrated graphics, security, system-on-a-chip (SOC) packaging options, etc. This 5-day course introduces the x86 Instruction Set Architecture (ISA) and describes the hardware features of the latest Intel Core and Xeon CPUs supporting it. In addition, the course presents an overview of memory, platform controller hub (PCH) logic, and IO interfaces that may be employed when implementing common system types.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>A full understanding of an Intel x86 hardware platform includes knowledge of CPU/PCH capabilities, BIOS/OS setup of programmable platform features, as well as the dynamic status of the system with regards to thermal and error events, etc. MindShare Arbor demonstrations integrated into this course present a decoded view of register setup, system and device status, as well as a coherent summary of platform information reported when the CPUID instruction is executed. Students may use Arbor software for real-time scans of local systems, read/modify specific registers, and even save Arbor scan results for later sharing and off-line review.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>This course is updated as frequently as possible in an attempt to provide a “snapshot” of Intel Core and Xeon x86 platform components and system implementations. Content is based on publicly available documents.\u003C/p>","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/x86proc_modules.png\" alt=\"PCIe Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/x86proc_slides.png\" alt=\"PDF Slides Thumbnail\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg style=\"max-height: 150px;\" src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/x86_cover_ds.png\" alt=\"PCIe eBook\" width=\"125\" height=\"155\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>Course eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>USB 3.0 eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"Intel Processors and Platforms\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","Jay Trodden","elearning@mindshare.com",5,120,"995",148,[],"\u003Cp>None.\u003C/p>","2025-08-05 14:37:08",1,57,{"id":39,"local_path":40,"file_name":41,"mime":16,"vimeo_uri":42,"duration":43,"thumbnail_filename":44,"local_thumbnail_path":45,"thumbnail_url":46},37741,"storage/app/videos/legacy/previews/","legacy-417348462.mp4","/videos/417348462",0,"Intel_x86_Processor_and_Platform_Architecture_eLearning_Course_thumbnail.png","storage/app/public/thumbnails/","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/Intel_x86_Processor_and_Platform_Architecture_eLearning_Course_thumbnail.png",[48],{"id":49,"name":50,"slug":51,"category_id":36,"author":16,"revision":52,"errata_text":16,"errata_link":16,"price":16,"file_path":53,"file_name":54,"cover_url":55,"peek_inside_file":16,"peek_inside_url":16,"overview":56,"has_book":57,"book_out_of_stock":57,"key_topics":58,"about_the_authors":59,"info":60,"authors":61,"publisher":62,"pages":63,"retail_price":64,"ebook_price":65,"book_price":66,"combined_price":66,"tags":67,"price_type":68,"related_items":69,"shipping_details":70,"is_active":13,"meta_title":16,"meta_description":73,"meta_keywords":74,"user_ebook":75},380,"x86 Instruction Set Architecture","x86-instruction-set-architecture","1.0","storage/app/ebooks/legacy/protected/","MindShare_x86_ISA_eBook_v1.0.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/x86_Instruction_Set_Architecture_cover-2025-06-30_15%3A22%3A18.png","\u003Cp>Wikipedia Definition: The Instruction Set Architecture, or ISA, is defined as that part of the processor architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external IO.\u003Cbr>\u003Cbr>Except for some small deviations and differences in terminology, all Intel and AMD x86 processors share a common ISA. This book focuses on those shared attributes (it does not cover those areas where the two companies have chosen widely divergent solutions, which, by definition, fall outside of the ISA specification).\u003Cbr>\u003Cbr>If you’re looking for a comprehensive book designed to bootstrap you up quickly on virtually all aspects of the x86 32/64-bit Instruction Set Architecture (ISA), we respectfully ask you to consider this book. Tom Shanley, President of MindShare, Inc., applied his 40 years of hardware and software experience with Intel processors (from the 4004 and 8008 through the Nehalem-based processors of today) to this ambitious undertaking. The material organization is derived from those used to train thousands of software and hardware designers at virtually all of the world’s leading high-tech companies.\u003C/p>",false,"\u003Cul>\r\n\u003Cli>Basic Terms and Concepts\u003C/li>\r\n\u003Cli>Mode/SubMode Introduction\u003C/li>\r\n\u003Cli>A (very) Brief History\u003C/li>\r\n\u003Cli>State After Reset\u003C/li>\r\n\u003Cli>Intro to the IA-32 Ecosystem\u003C/li>\r\n\u003Cli>Instruction Set Expansion\u003C/li>\r\n\u003Cli>32-bit Machine Language Instruction Format\u003C/li>\r\n\u003Cli>Real Mode (8086 Emulation)\u003C/li>\r\n\u003Cli>Legacy x87 FP Support\u003C/li>\r\n\u003Cli>Introduction to Multitasking\u003C/li>\r\n\u003Cli>Multitasking-Related Issues\u003C/li>\r\n\u003Cli>Summary of the Protection Mechanisms\u003C/li>\r\n\u003Cli>Protected Mode Memory Addressing\u003C/li>\r\n\u003Cli>Code, Calls and Privilege Checks\u003C/li>\r\n\u003Cli>Data and Stack Segments\u003C/li>\r\n\u003Cli>IA-32 Address Translation Mechanisms\u003C/li>\r\n\u003Cli>Memory Type Configuration\u003C/li>\r\n\u003Cli>Task Switching\u003C/li>\r\n\u003Cli>Protected Mode Interrupts and Exceptions\u003C/li>\r\n\u003Cli>Virtual 8086 Mode\u003C/li>\r\n\u003Cli>The MMX Facilities\u003C/li>\r\n\u003Cli>The SSE Facilities\u003C/li>\r\n\u003Cli>IA-32e OS Environment\u003C/li>\r\n\u003Cli>IA-32e Address Translation\u003C/li>\r\n\u003Cli>Compatibility Mode\u003C/li>\r\n\u003Cli>64-bit Register Overview\u003C/li>\r\n\u003Cli>64-bit Operands and Addressing\u003C/li>\r\n\u003Cli>64-bit Machine Language Instruction Format\u003C/li>\r\n\u003Cli>64-bit Odds and Ends\u003C/li>\r\n\u003Cli>Transitioning to Protected Mode\u003C/li>\r\n\u003Cli>Transitioning to IA-32e Mode\u003C/li>\r\n\u003Cli>Introduction to Virtualization Technology\u003C/li>\r\n\u003Cli>System Management Mode (SMM)\u003C/li>\r\n\u003Cli>Machine Check Architecture (MCA)\u003C/li>\r\n\u003Cli>The Local and IO APICs\u003C/li>\r\n\u003C/ul>","\u003Cp>\u003Cstrong>Tom Shanley\u003C/strong>, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.\u003C/p>","\u003Cp>Processor design-specific subjects such as Power Management and design-specific MSRs are not covered in this book. Rather, they are covered in MindShare's Processor family-specific microarchitecture classes.\u003C/p>\r\n\u003Cp>MindShare's System Architecture Series is a crisply written and comprehensive set of guides to the most important computer hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel.\u003C/p>","Tom Shanley","MindShare Press",1567,"99.99","40","0",[],"ebook_price",[],{"book_width":71,"book_length":71,"book_height":71,"book_weight":72},0.01,0.008,"MindShare x86 Instruction Set Architecture","x86, intel architecture, amd64, ia-32, intel 64, book, ebook, e-book",{"id":76,"presentation_id":16,"downloaded":57,"signed_file_name":16,"watermark_status":77,"is_new":57,"revision":16},93253,"WATERMARK_NOT_CREATED",[79,87,94],{"id":80,"course_name":81,"classroom_info":15,"virtual_classroom_info":82,"file_url":83,"course_link":84,"link":85,"file_name":86},160,"Intel x86 Processor and Platform Architecture","10 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_Intel_ProcPlat_Agenda.pdf","/live-training-course/intel-processor-and-platform-architecture","/elearning-course/intel-x86-processor-and-platform-architecture-elearning-course","MindShare_Intel_ProcPlat_Agenda.pdf",{"id":88,"course_name":89,"classroom_info":15,"virtual_classroom_info":82,"file_url":90,"course_link":91,"link":92,"file_name":93},176,"x86 64-bit Architecture","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_x86_Architecture_Outline.pdf","/live-training-course/x86-64bit-architecture","/elearning-course/x86-architecture-elearning-course","MindShare_x86_Architecture_Outline.pdf",{"id":95,"course_name":96,"classroom_info":97,"virtual_classroom_info":98,"file_url":99,"course_link":100,"link":101,"file_name":102},171,"UEFI x64 Architecture eLearning Course","4 days","8 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_UEFI_Agenda.pdf","/live-training-course/uefi-architecture","/elearning-course/uefi-x64-architecture-elearning-course","MindShare_UEFI_Agenda.pdf",[104],{"id":105,"comment":106},87,"\"This course is good for general understanding for the Intel platform architecture as well as to familiarize people with commonly seen elements for an Intel platform: the PCH, APICs, PCIe, MSIs, cache, microarchitectures, various peripherals and so on.\" - Leo",1793108630370]