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the Technology Brief
  in this issue
  eLEARNING COURSES   USB 3.0 Architecture
  PUBLIC COURSES   Modern DRAM, PCI Express®, USB 3.0.
  TECHNICAL WHITEPAPERS   USB 3.0 Retransmission Mech.
  BOOKS + eBOOKS   x86 Instruction Set Architecture
  COURSE LIST  Intel® QPI, Intel® Nehalem, USB 3.0.....
  NEWSROOM   MindShare Announces New Courses
  MINDSHARE BROCHURE   View MindShare's New Brochure

Featured eLearning Course  New - Just Released
Comprehensive USB 3.0 Architecture

  Instructor Don Anderson
  Price $895
Other eLearning Courses Available
Comprehensive Modern DRAM (DDR2/DDR3) Architecture
Comprehensive PCI Express® 2.0 Architecture
Comprehensive USB 2.0 Architecture
Comprehensive SATA Architecture
Comprehensive SAS Architecture

PCI Express® 2.1 and 3.0 Updates
Fundamentals of PCI Express®
Fundamentals of Intel® QuickPath Interconnect

Intro to 32/64-bit x86 Architecture
Intro to PCI Express® IO Virtualization
Intro to Virtualization Technology
Intro to PCI Express® 2.0 Changes


Public Courses

Q2 2010 Courses

  USB 3.0 Architecture in 1 week  
  Dates 06/01/10 - 06/04/10  
  Price $2495  
  Location Milpitas, CA - Classroom   
   Modern DRAM (DDR2/3) Architecture  
  Dates 06/10/10 - 06/11/10
  Price $1195  
  Location Santa Clara, CA - Classroom   
  PCI Express® 2.0 Architecture  
  Dates 06/14/10 - 06/17  
  Price $2495  
  Location Santa Clara, CA - Classroom  


View All Available Classes

  Featured Book + eBook  New
x86 Instruction Set Architecture
    HyperTransport 3.1 Interconnect

Click Book Thumbnail to preview Book

  Author Tom Shanley
  Publisher MindShare Press
  Price Book   $89.99
eBook $42.00

Other Books
SATA Storage Technology
SAS Storage Technology
HyperTransport 3.1 Interconnect Technology
PCI Express® System Architecture
The Unabridged Pentium 4
USB System Architecture

Featured Article
USB 3.0 Link Layer & Protocol Layer Retransmission Mechanism


by Ellisys

  USB 3.0 retransmission mechanisms are quite different from USB 2.0 because of the new routing infrastructure. USB 3.0 has separate retransmission mechanisms in the Link and the Protocol Layers for optimizing data buffering in devices and especially hubs. This white paper examines traffic exchanged between two link partners (such as a host and a device) when a DPH is received as invalid by one end.


Other Resources and Articles


- Introduction to USB 3.0 Architecture

- Overview of Changes to PCI Express® 2.1 and 3.0

- Introduction to PCI Express®

- PCI Express® Measurement Poster

- EHCI for USB 2.0



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