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USB 4.0 eLearning Course Info
What's Included?
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USB 4.0 eLearning Modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
USB 3.0 eBook
(yours to keep, does not expire) |
Benefits of eLearning:
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
- Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
You Will Learn:
- How a Type-C port determines it should operate as USB4
- Details of tunneling PCIe, DisplayPort and USB3 (ESS) across USB4 links
- How the Connection Manager discovers and enumerates USB4 Routers
- Interaction between the Host I/F Adapter and the Connection Manager using Tx and Rx Rings
- Routing of USB4 TLPs based on HopID and routing tables
- Flow control schemes employed in USB4
- Low-level initialization and training of a USB4 link
If you are going to take one course on USB4, this should be it. MindShare's USB4 eLearning course is an exhaustive tutorial on USB4 from the electrical PHY all the way up to the Connection Manager (CM). It starts with a high-level view of the architecture, including the background of Thunderbolt to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols.
Who Should View?
This course is hardware-oriented but is suitable for both hardware and software engineers because the configuration registers used to control the hardware and advertise its capabilities and status are covered in detail. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of USB4. Because the course contains practical examples of transactions on the various bus interfaces, the course is also suitable for chip-level and board-level validation engineers.
USB 4.0 Module Descriptions:
- Module 1: Introduction
- Goes over course outline and what to expect
- Module 2a: USB4 Overview: Background
- Why USB4?, Thunderbolt evolution (TBT1, TBT2 and TBT3)
- Module 2b: USB4 Overview: Background
- USB-C port and its introduction with Thunderbolt 3
- Module 3a: USB4 Overview: Fabric Elements
- USB4 point-to-point links, link speeds, router types and their requirements (host, hub, peripheral and dock), USB4 topology rules
- Module 3b: USB4 Overview: Fabric Elements
- Adapter types within routers: Host I/F adapters, protocol adapters, lane adapters, control adapters
- Module 3c: USB4 Overview: Fabric Elements
- USB-C connector basics: Tx1/Rx1, Tx2/Rx2, SBTX/SBRX, Dp1/Dn1, VBUS, VCONN, CC, bypass mux logic with examples
- Module 4a: USB4 Overview: Protocol Tunneling and Functional Layers
- Intro to tunneling of PCIe, DisplayPort and USB3, defining USB4 functional layers and mapping of adapters
- Module 4b: USB4 Overview: Protocol Tunneling and Functional Layers
- Intro to Connection Manager (CM) and Host Interface (I/F) adapter and their interaction, show detailed functionality per layer
- Module 4c: USB4 Overview: Protocol Tunneling and Functional Layers
- Transport Layer Packets (TLPS): Control, Tunneled and Link Management Packets; TLP packet format, HopID and Paths
- Module 4d: USB4 Overview: Protocol Tunneling and Functional Layers
- Intro to flow control and Quality of Service (QoS), idle packets, discussion about the inefficiencies of tunneling other protocols
- Module 5a: Transport Layer Packets (TLPs) and TLP Routing
- TLP format, TLP header fields, TLP sizes, Control packet route string
- Module 5b: Transport Layer Packets (TLPs) and TLP Routing
- Examples of routing control packets
- Module 5c: Transport Layer Packets (TLPs) and TLP Routing
- Defining Paths, HopID assignment and use in Routing Tables, example tunneled traffic routing for PCIe, USB3 and DP, Link Management packets, need for idle packets, minimum gap header requirements
- Module 6a: QoS: Flow Control and Arbitration
- Ordering rules, flow control credit, flow control schemes (disabled, dedicated, shared, restricted shared), example FC setup, flow control buffer groups (disabled, dedicated and shared)
- Module 6b: QoS: Flow Control and Arbitration
- Flow control tracking (credit limit, credits consumed, credits allocated, credits received), credit grant packets, credit grant records, credit sync packet, numerous flow control examples
- Module 6c: QoS: Flow Control and Arbitration
- Strict priority of traffic at link scheduler, priority groups and assignment, weight assignment, no automatic retries, notification packets, error detection and correction
- Module 7a: USB3 Tunneling
- USB 3.2 background: dual bus topology, bandwidth options, host controllers, hubs, endpoints, layered protocol model, traffic types
- Module 7b: USB3 Tunneling
USB4 fabric resources for USB3 tunneling, USB3 tunneling support: USB4 host, hub, peripheral, USB 3.2 ESS Transaction Packet tunneling, USB 3.2 ESS Data Packet tunneling (small payloads)
- Module 7c: USB3 Tunneling
Segmented Data Packet tunneling, Tunneling ESS Link Commands, Tunneling ESS Ordered Sets, Tunneling ESS LFPS events
- Module 8a: PCIe Tunneling
- Background info on PCIe, PCIe device layers, functionality not needed for tunneling across USB4, LTSSM modifications, PCIe traffic types
- Module 8b: PCIe Tunneling
- PDF values for PCIe, pre-header format and purpose, packing in USB4 payloads
- Module 8c: PCIe Tunneling
- PCIe logical and electrical idle in USB4, PCIe resets in USB4, additional PCIe requirements within USB4 systems
- Module 9a: DisplayPort Tunneling
- DisplayPort (DP) background info, Main Link, Aux Link, Hot Plug Detect (HPD), Main Path PDF values, DP SST vs MST, SST video data packets, transfer units (TU), TU set header
- Module 9b: DisplayPort Tunneling
- Aux path PDF values, HPD packets, ACK packets, AUX packets, DP Link Training Tunable PHY Repeater (LTTPR), DP adapter operational modes: LTTPR Non-Transparent Mode, LTTPR Transparent Mode, Non-LTTPR Mode, SET_CONFIG packets
- Module 10a: Configuration Spaces
- Four types of USB4 config space: Router, Adapter, Path and Counter; router basic registers, USB4 router operations, router capability structures: TMU and Vendor Specific
- Module 10b: Configuration Spaces
- Adapter config space, basic registers, capability structures per adapter type, path config space, counter config space
- Module 10c: Configuration Spaces
- Sideband register space, port operations
- Module 11a: Host Interface
- Role of the Host I/F in providing Connection Manager access to the USB4 fabric, resources required by the Host I/F: PCI registers, MMIO registers, main memory resources
- Module 11b: Host Interface
- Covers USB4 Tx and Tx Ring basics: motivation, Tx/Rx Ring and HopID mapping, populating Tx/Rx Rings with descriptors, data buffers, Raw Mode vs Frame Mode
- Module 11c: Host Interface
- Transmit (Tx) Ring details: Tx descriptor ring registers, Tx Ring descriptor format
- Module 11d: Host Interface
- Receive (Rx) Ring details: Rx descriptor ring registers, Rx Ring descriptor format
- Module 12a: USB4 Interrupts
- Interrupt background, MSI basics, advantages of MSI-X, setting up Host I/F MSI vs MSI-X
- Module 12b: USB4 Interrupts
- Host I/F interrupt sources, interrupt registers and usage models, interrupt status, interrupt mask (IMR), interrupt throttling rate (ITR), interrupt vector allocation (IVAR), receive ring vacancy
- Module 13a: Physical Layer - Introduction
- USB4 port and link support logic, TLP traffic review, other USB4 traffic: ordered sets and LFPS, Sideband transactions, power delivery messages
- Module 13b: Physical Layer - Introduction
- Connection Manager and lane adapter state machine (LASM) roles, key lane adapter configuration spaces, sideband interface register set
- Module 13c: Physical Layer - Introduction
- USB-C cables for USB4, active vs. passive electronically marked cables, VCONN cable power, re-timer options
- Module 14a: Physical Layer - Logical
- Logical layer processing of outbound TLPs and ordered sets: lane distribution (striping), symbol encoding, bit order swap, scrambling, skip insertion, RS-FEC encoding, pre-coding
- Module 14b: Physical Layer - Logical
- Logical layer processing of inbound TLPs and ordered sets: pre-coding removal, RE-FEC decoding, skip removal, de-scrambling, bit order restore, symbol decoding
- Module 15a: Physical Layer - Electrical
- Scope of USB4 electrical layer requirements, sideband interface signals, high speed signals
- Module 15b: Physical Layer - Electrical
- Equalization background, Transmitter 3-tap Finite Impulse Response (FIR) filter equalization, Receiver Continuous Time Linear Equalizer (CTLE) and single-tap Decision Feedback Equalizer (DFE)
- Module 15c: Physical Layer - Electrical
- Router assembly compliance test points, Tx/Rx signal requirements, SSC and LFPS
- Module 16a: Link Initialization and Training
- Type-C Port Manager (TCPM) and the USB-C Port Controller roles, CM and its register interface, Link Layer State Machine: Training State, five phases of link initialization
- Module 16b: Link Initialization and Training
- USB-C Configuration Channel (CC), determining the default DFP/UFP & VBUS source/sink, resolving plug orientation, detecting an electronically marked cable, DFP advertisement of default VBUS power
- Module 16c: Link Initialization and Training
- Power contract negotiation, source capabilities PD message: VBUS choices; sink request PD message, source confirms, renegotiation options
- Module 16d: Link Initialization and Training
- USB4 operational mode discovery, operational mode entry, miscellaneous phase 1 tasks
- Module 16e: Link Initialization and Training
- Covers initialization phase 2 through phase 4
- Module 16f: Link Initialization and Training
- Covers initialization phase 5 and remainder of USB4 link training
- Module 17: Time Synchronization
- Introduces purpose of establishing a common time domain across devices, local clock per router (associated with TMU), bi-directional mode vs uni-directional mode, HiFi resolution vs LowRes, TSNOS and Follow Up link management packets, synchronization process, explanation of equations involved for time offset and frequency offset calculations with examples
- Module 18: USB4 Link Low Power States
- Lane Adapter State Machine and low power states, Connection Manager register interface, Low power state entry and exit, Link low power exit and the re timers
- Module 19: Thunderbolt3 Interoperability
- Required/optional TBT3 support for USB4 hosts, hubs, and peripherals, Gen 2/Gen 3 TBT3 link speeds, Transport Layer changes for TBT3, Router Configuration Space register additions, Lane Adapter State Machine (LASM) changes, TBT3 Sideband interface differences
 | Course Modules |
| Module | Length | | Module 1: Course Intro | 17 minutes | | Module 2a: USB4 Overview: Background, Part A | 46 minutes | | Module 2b: USB4 Overview: Background, Part B | 36 minutes | | Module 3a: USB4 Overview: Fabric Elements, Part A | 43 minutes | | Module 3b: USB4 Overview: Fabric Elements, Part B | 31 minutes | | Module 3c: USB4 Overview: Fabric Elements, Part C | 44 minutes | | Module 4a: USB4 Overview: Protocol Tunneling and Functional Layers | 36 minutes | | Module 4b: USB4 Overview: Protocol Tunneling and Functional Layers | 37 minutes | | Module 4c: USB4 Overview: Protocol Tunneling and Functional Layers | 34 minutes | | Module 4d: USB4 Overview: Protocol Tunneling and Functional Layers | 33 minutes | | Module 5a: Transport Layer Packets (TLPs) and TLP Routing | 42 minutes | | Module 5b: Transport Layer Packets (TLPs) and TLP Routing | 21 minutes | | Module 5c: Transport Layer Packets (TLPs) and TLP Routing | 41 minutes | | Module 6a: QoS: Flow Control and Arbitration | 31 minutes | | Module 6b: QoS: Flow Control and Arbitration | 34 minutes | | Module 6c: QoS: Flow Control and Arbitration | 21 minutes | | Module 7a: USB3 Tunneling, Part A | 41 minutes | | Module 7b: USB3 Tunneling, Part B | 38 minutes | | Module 7c: USB3 Tunneling, Part C | 52 minutes | | Module 8a: PCIe Tunneling | 35 minutes | | Module 8b: PCIe Tunneling | 37 minutes | | Module 8c: PCIe Tunneling | 36 minutes | | Module 9a: DisplayPort Tunneling | 39 minutes | | Module 9b: DisplayPort Tunneling | 49 minutes | | Module 10a: Configuration Spaces | 34 minutes | | Module 10b: Configuration Spaces | 31 minutes | | Module 10c: Configuration Spaces | 10 minutes | | Module 11a: Host Interface, Part A | 25 minutes | | Module 11b: Host Interface, Part B | 29 minutes | | Module 11c: Host Interface, Part C | 30 minutes | | Module 11d: Host Interface, Part D | 40 minutes | | Module 12a: USB4 Interrupts, Part A | 38 minutes | | Module 12b: USB4 Interrupts, Part B | 41 minutes | | Module 13a: Physical Layer-Introduction, Part A | 32 minutes | | Module 13b: Physical Layer-Introduction, Part B | 35 minutes | | Module 13c: Physical Layer-Introduction, Part C | 27 minutes | | Module 14a: Physical Layer-Logical, Part A | 42 minutes | | Module 14b: Physical Layer-Logical, Part B | 22 minutes | | Module 15a: Physical Layer-Electrical, Part A | 22 minutes | | Module 15b: Physical Layer-Electrical, Part B | 18 minutes | | Module 15c: Physical Layer-Electrical, Part C | 27 minutes | | Module 16a: Link Initialization and Training, Part A | 25 minutes | | Module 16b: Link Initialization and Training, Part B | 24 minutes | | Module 16c: Link Initialization and Training, Part C | 13 minutes | | Module 16d: Link Initialization and Training, Part D | 28 minutes | | Module 16e: Link Initialization and Training, Part E | 27 minutes | | Module 16f: Link Initialization and Training, Part F | 43 minutes | | Module 17: Time Synchronization | 53 minutes | | Module 18: USB4 Link Low Power States | 28 minutes | | Module 19: Thunderbolt3 Interoperability | 30 minutes | | |
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