PCI Express 3.0 - Hands-On 4-Day Course
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PCI Express 3.0 - Hands-On 4-Day Course
(Santa Clara, CA: 9/18/2017)

PCI Express - Fundamentals 1-Day Course
(Santa Clara, CA: 9/18/2017)

NVM Express (NVMe) 1.3 - Hands-On 1-Day Course
(Santa Clara, CA: 9/22/2017)






PCI Express 3.0 - Hands-On 4-Day Course

Location Santa Clara, CA
Date 9/18/2017 - 9/21/2017
Duration 4-day
Instructor Michael Jackson
Sponsor Teledyne LeCroy
Price $2,995.00

Hands-On PCI Express 3.0 Training Details:

MindShare's PCI Express System Architecture course starts with a high-level view of the design to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols.

This course describes additional features added to the architecture when moving from PCIe specification revision 1.1 to 2.0 to 2.1 to 3.0 . PCIe 3.0 (Gen 3) doubles the bandwidth available in revision 2.0 (Gen 2) by increasing the transfer rate and dropping 8b/10b encoding. But a number of protocol changes were also implemented in the change from revision 2.0 to 2.1, and those are described, too. The Gen 3 changes are physical layer updates to support the higher speed and some new steps that were needed for link training to get that speed working reliably, but the upper layers are left unchanged.

You Will Learn:

  • Features of PCIe Gen1, Gen2, Gen3
  • The definition and responsibilities of each of the layers in the interface
  • How the hardware-based automatic error detection and correction mechanism works
  • The various additional levels of error detection and reporting
  • The details of the packet-based protocol used by PCIe
  • The address space and packet-routing methods used
  • How the various power management techniques work
  • The details of the configuration registers that provide control and status visibility to software
  • What changes are needed to run the link at 8.0GT/s (rev 3.0 speeds)

Course Length: 4-Days

Times:

Start time each day: 9:00am
End time each day: 5:30pm
Lunch provided between noon-1:00pm. AM and PM snacks and beverages

Location:

Summit Conference Room
TeledyneLeCroy Corporation
3385 Scott Boulevard
Santa Clara, CA 95054

Who Should Attend?

This in-depth course is hardware oriented, but is designed for both hardware and software engineers. The course contains numerous practical examples of transactions on the link, including relevant analyzer captures of some error conditions. It also covers the rules required for a device to be compliant with the spec. This makes the course ideal for system validation engineers who are evaluating an RTL-level, chip-level, system-level or system board-level design.

Course Outline:

  • PCI Architecture Background Foundation
    • PCI Legacy Configuration Transaction Generation
  • PCI Express Features and Architecture Overview
    • Layered Architecture
    • TLP, DLLP and Ordered Set Packet Format Overview
    • Protocol Overview
    • PCI Express Memory-Mapped Configuration Transaction Generation
  • Configuration Space Overview
  • Packet Format Details
    • TLP
    • DLLP
  • Address Space and Transaction Routing
    • Switch Routing Mechanism
  • Quality of Service and Arbitration Overview
    • TC/VC Mapping and VC/Port Arbitration
  • Flow Control
    • Flow Control Initialization
    • Runtime Flow Control Update Mechanism
  • Transaction Ordering
    • ID-Based ordering (2.1)
    • Simplified ordering table (2.1)
  • ACK/NAK Protocol
    • Error Recovery Mechanism
    • Examples of Variety of Error Scenarios
    • Nullified Packets and Store-and Forward vs. Cut-Through Mode
  • Physical Layer Logic Gen1, Gen2, Gen3
    • Byte Striping/Unstriping
    • Scrambling/Unscambling
    • 8b/10b and 128b/130b Encoding/Decoding
    • Serializing/Deserializing
  • Error Detection and Handling
    • Correctable, Non-Fatal and Fatal Errors
  • System Resets
    • Fundamental Reset, Inband Reset, Function Level Reset
  • Link Initialization & Link Training
    • Detect, Polling, Configuration, L0 states
    • Power Management States: L0, L0s, L1, L1 Active, L2, L3 Power States
    • Dynamic Link Width and Speed Changes between 2.5 and 5.0 GT/s
  • Physical Layer Electrical Gen1, Gen2, Gen3
    • Electrical Changes for Gen2 and Equalization for Gen3
  • Power Management (optionally covered)
    • Software controlled Power Management
    • Active Hardware-based Power Management
    • Latency Tolerance Reporting (2.1) and L1 substates (3.1)
  • Interrupt Support
    • Legacy Interrupt Handling
    • MSI Interrupt
    • MSI-X Interrupt

Recommended Prerequisites:

A solid understanding of one or more bus protocols such as PCI or similar architecture is highly recommended but not required.

Training Materials:

1) MindShare will supply a copy of the "PCI Express Technology " eBook by Mike Jackson and Ravi Budruk

2) License to MindShare Arbor Software learning/debug tool

3) Downloadable PDF version of the presentation slides

PCI Express® is a registered trademark of the PCI-SIG