Compute Express Link (CXL) 3.0 - Comprehensive 5-day Course
View all Public Courses

All Available Public Courses
DRAM (DDR5/LPDDR5) - Comprehensive 4-Day Course
(US Pacific Time, 9am-5pm: 4/23/2024)

Compute Express Link (CXL) 3.0 - Comprehensive 5-day Course
(US Pacific Time, 9am-5pm: 5/6/2024)

PCI Express Security - 5 Half-Day Course
(US Pacific Time, 1pm-5pm: 5/13/2024)






Compute Express Link (CXL) 3.0 - Comprehensive 5-day Course

Location US Pacific Time, 9am-5pm
Date 5/6/2024 - 5/10/2024
Duration 5-Days
Instructor Ravi Budruk
Price $3,495.00

Comprehensive CXL 2.0 self-paced eLearning video course included in training fees 

Comprehensive Compute Express Link (CXL) 3.0 Architecture Course Details:

Compute Express Link (CXL) is a high-bandwidth, low-latency serial bus interconnect between host processors and devices such as accelerators, memory controllers/buffers, and I/O devices. CXL 3.0 is based on PCI Express® (PCIe®) 6.0 physical layer running at 64 GT/s with x16, x8 and x4 link widths. Degraded modes run at 32GT/s, 16 GT/s and 8 GT/s with x2 and x1 link widths.

CXL interconnect adds coherency and memory semantics, thus allowing for its application in heterogeneous processing systems with a variety of host processors, memory subsystems and peripheral devices interconnected. CXL has applications in standard computer systems, Artificial Intelligence (AI), Machine Learning, communication systems, and High-Performance Computing (HPC). Emerging applications require a diverse mix of CPUs, GPUs, FPGAs, peripherals such as smart NICs, and other accelerators interconnected via an open industry standard protocol with the necessary features which CXL provides. CXL provides a rich set of three protocols that include 1) CXL.io based on PCIe TLP based transactions, 2) CXL.cache and 3) CXL.mem semantics. CXL uses the PCIe stack offering full interoperability with PCIe. CXL.cachemem protocols allow for coherent transactions in memory space. These transactions employ Flit-based packet routing on the Link.

MindShare’s comprehensive CXL 3.0 Architecture course provides a solid foundation of platform architectures and use cases of the three CXL protocols with Type 1, Type 2 and Type 3 devices in platform example. The course details the role of the Transaction Layer protocol, Link Layer including Flit packing and unpacking, ARB/MUX and Flex Bus Logical and Electrical Physical Layer of a CXL port design. We explain enumeration and configuration process during system bring-up with details of configuration and component registers. Other topics include switch architecture overview, reset, manageability, RAS features, power management, performance considerations and compliance testing. The course describes new features added to the CXL 3.0 spec such as 256B and Port Based Routing (PBR) Flits, CXL.mem Back-Invalidation, Dynamic Capacity Devices (DCD), LD-FAM and G-FAM Devices, Global Integrated Memory (GIM), Multi-Headed (MH) Devices, Hierarchy Based Routing (HBR) and Port Based Routing (PBR), Direct Peer-to-Peer Routing and lots more.

You Will Learn:

  • CXL system architectures with Type 1, Type 2 and Type 3 devices
  • CXL transaction protocol (CXL.io and CXL.cache/mem)
  • CXL port design constituting Transaction, Link, ARB/MUX and Flex Bus Physical Layers
  • CXL 3.0 spec added features such as 256B HBR and PBR Flit formats, Back-Invalidation, LD-FAM, G-FAM, DCD Devices etc.
  • Enumeration and initialization issues with configuration register definitions
  • Power management
  • Reliability, Availability, Serviceability (RAS) and error handling features
  • CXL Switch architecture Overview
  • Variety of Resets
  • CXL register architecture

Course Length: 5-Days

US Pacific Time Zone Times:

Start time: 9:00am US Pacific Time
End time: 5:00pm  US Pacific Time, 45min lunch break 12:30-1:15pm

Location:

Virtual-Classroom US Pacific Time Zone, 9am-5pm

Who Should Attend?

This course is hardware-oriented, but is suitable for both hardware design and software engineers given the course covers CXL initialization topics. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of CXL architecture. The course is also suitable for chip-level and board-level validation engineers.

Course Outline:

  • CXL Features and Architecture Overview
    • Limitations of interconnects that do not support coherency and memory semantics
    • CXL and Flex Bus Link features
    • CXL.io, CXL.cache, CXL.mem protocol overview
    • Type 1 (devices with cache), Type 2 (devices with cache and memory) and Type 3 (memory expander) devices
    • Layered architecture overview
    • CXL 3.0 added features overview
    • Example Transaction Flows
  • CXL Transaction Layer
    • CXL.mem protocol including CXL 3.0 Back Invalidation protocol
    • CXL.cache protocol including Device Scaling
    • CXL.io protocol
    • Transaction Ordering
  • CXL Link Layer
    • CXL.io Link Layer
    • CXL.cache and CXL.mem common Link Layer
    • Flit packets inlcuding 256B HBR and PBR Flit formats added to CXL 3.0 spec.
    • Link Layer initialization (LLI)
    • CXL.cache/mem packets flow control including CXL 3.0 Flow Control mechanism
    • CXL 2.0 retry mechanism. (Retry mechanism for 256B Flit mode is covered in MindShare's PCIe 6.0 course)
    • CXL.cache viral feature
  • CXL ARB/MUX Layer
    • Virtual Link State Machine (vLSM) states
    • ARB/MUX Link Management packets (ALMPs)
  • Flex Bus Physical Layer
    • Protocol ID and Flit packet layout
    • Byte Striping
    • NOP Flits, IDLE Flits, Latency Optimized Flits
    • Sync Header Bypass (Latecy Optimization) mode
    • Link training including changes in the CXL 3.0 spec.
  • Resets
    • Cold reset
    • Warm reset
    • Hot Reset
    • Function Level reset (FLR)
    • CXL Reset
  • RAS and Error Handling
    • RAS features
    • Link Down handling
    • Viral handling
    • Memory Error Firmware Notification (MEFN) feature
  • Enumeration, Manageability and Memory Interleaving
  • CXL Control and Status related registers
    • DVSEC Configuration and Status registers
    • CompiMemory Mapped registers
    • CXL 3.0 spec added registers
  • CXL 3.0 Spec added Device Types
    • LD-FAM, G-FAM
    • Dynamic Capacity Device (DCD)
    • Shared vs Pooled Memory

Recommended Prerequisites:

Complete working knowledge of PCI Express architecture. Computer architecture fundamentals. Cache coherency concepts incuding MESI protocol

Training Materials: