PCI Express Security - 5 Half-Day Course
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PCI Express Security - 5 Half-Day Course
(US Pacific Time, 1pm-5pm: 5/13/2024)






PCI Express Security - 5 Half-Day Course

Location US Pacific Time, 1pm-5pm
Date 5/13/2024 - 5/17/2024
Duration 5 Half-Days
Instructor Paul Devriendt
Price $2,295.00

PCIe Security self-paced eLearning video course included in training fees

PCI Express Security Course Details:

The threat model for PC systems has changed dramatically over the years. Inserting a card (e.g., AGP, PCI, PCI-X, PCIe) was an action that required physical access to the system board, and the system could be protected with a case lock and intrusion alarms. It was regarded that a plug-in card that the user chose to install in their system should therefore be trusted. There have been many changes to this simple picture that result in a very different threat model today.

This PCIe focused security course starts by looking at some of the simpler forms of attacks such as DMA, and some of the defenses again those attacks (IOMMU), and also some of the holes in these defense mechanisms. We then move onto looking at some of the additional features added to help protect the fabric (such as source validation in Access Control Services), and then onto the newest features for evaluating trust, link encryption, and point-to-point encryption. We also look at the supported for a TEE (Trusted Execution Environment) VM.

This is not a platform security course as there are many other topics of relevance to security that we will not discuss, such as UEFI, hypervisors, operating systems, processor security features, etc.

This class looks at potential attacks on “legacy” PCIe and some of the mitigations (ACS, IOMMU, etc), and then explores the newer features (CMA, IDE, SPDM, TDISP, etc). This class is based on the ECNs to PCIe 4.0 and 5.0, and also covers the changes from PCIe 6.0 and 6.1. 

Course Length: 5 Half-Days

US Pacific Time Zone Times:

Start time each day: 1:00pm US Pacific Timezone
End time each day: 5:00pm US Pacific Timezone

Location:

Virtual-Classroom US Pacific Timezone

Who Should Attend?

This in-depth course is hardware oriented, but is designed for both hardware and software engineers. It also covers the rules required for a device to be compliant with the spec. This makes the course ideal for system validation engineers who are evaluating an RTL-level, chip-level, system-level or system board-level design.

Course Outline:

  • Early systems. The necessity for the proliferation of DMA engines. The necessity for interrupts.
  • Address spaces, such that memory may be readable/writeable memory, or may be I/O space.
  • DMA attacks, copying or modifying memory.
  • Malicious hardware entering the supply chain.
  • Mutable versus immutable, and the surprises.
  • Impersonation (where a device pretends to be something else).
  • Convergence and convenience (USB-C for charging but also for attacking).
  • Use of an IOMMU to prevent DMA attacks.
  • IOMMU issues at boot time versus runtime, setup and configuration of the IOMMU, and the ACPI tables.
    PCIe defined ATC as a bypass for the IOMMU.
  • PCIe defined ACS as a mitigation for the ATC.
  • Error reporting from devices.
  • Congestion based attacks.
  • Interrupt based attacks, with the interrupt remapping as mitigation.
  • NMI and SMI bypass to the interrupt remapping.
  • Fabric based attacks (watching links, changing packets, injecting packets) from the switch.
  • Fabric based attacks from retimers.
  • The need for
    • Establishing trust (host knowing the device, device knowing the host).
    • Key exchange.
    • Encrypted links.
  • Keys, certificates and encryption background
    • public and private keys
    • encryption standards
    • certificates
    • X.509 trust model
    • AES-GCM
  • IDE (Integrity and Data Encryption)
    • Link security threat model
    • Exposures not covered by the threat model
    • Link IDE
    • The switch as an attack vector
    • Selective IDE
    • Mixing Link and Selective IDE
    • Stream establishment
    • Side channel attacks via unencrypted headers
    • IDE TLPs
    • TLP Encryption
    • TLP Aggregation
    • IDE Extended Capability structure
    • IDE Sub-Streams
    • Power management and resets
    • Error conditions and error reporting
    • Partial header encryption with PCIe 6.0
    • Segments with PCIe 6.0
    • Link and selective IDE with Flit Mode (PCIe 6.0)
    • IDE may not be sufficient, what else may be needed
      • key exchange
      • trust
  • PCI-SIG and DMTF Specifications overview
  • TCG (Trusted Computing Group) background
    • root of trust
    • attestation
    • system startup
  • CMA/SPDM (Component Measurement and Authentication / Security Protocol and Data Model
    • multiple paths to PCIe devices (SMbus, I2C)
    • threat model
    • mutable and immutable objects
    • authentication
    • TLS (Transport Layer Security) background
    • attestation
    • recommended flow
    • handling versions
    • certificates and chains of certificates
    • mutual authentication
    • session key exchange
    • Diffie-Hellman scheme background
    • PSK (pre-shared key)
    • secure session
    • provisioning
    • alias certificates (dynamic certificates)
    • complications of having 2 certificate models
    • open source libspdw, a sample implementation
  • IDE_KM (IDE Key Management)
    • Key management messages over SPDM
    • Root port handling
  • DOE (Data Object Exchange)
    • Mailboxes and their use
    • DOE Extended Capability structure
    • DOE Capabilities registers
    • DOE Interrupts
  • MCTP (Management Component Transport Protocol)
    • manageability traffic and the pre-boot environment
    • transport bindings
    • messages
    • packets
    • endpoints and EIDs (endpoint IDs)
    • the MCTM Bus Manager
    • SPDM over MCTP Binding
    • Secured MCTP Messages over MCTP Binding
  • MCTP over SMBus and I2C
  • MCTP over PCIe, and PCIe VDMs
  • TDISP (TEE Device Interface Security Protocol)
  • Summary, putting it all together

Recommended Prerequisites:

A good understanding of PCI Epress Architecture or completion of MindShare's PCIe 5.0 live- or eLearning- courses.

Training Materials:

  1. MindShare eBook PCI Express Technology 3.0 by Mike Jackson and Ravi Budruk
  2. PDF version of the presentation slides used in class
  3. PCIe Security eLearning course which is used to review the material covered in class post course completion

PCI Express® is a registered trademark of the PCI-SIG