Compute Express Link (CXL) - Fundamentals 1-Day Course
Location 9am-5pm PST (California Time)
Date 12/7/2021 - 12/7/2021
Instructor Ravi Budruk
Fundamentals of Compute Express Link (CXL) Architecture Course Details:
Compute Express Link (CXL) is a high-bandwidth, low-latency serial bus interconnect between host processors and devices such as accelerators, memory controllers/buffers, and I/O devices. CXL is based on PCI Express® (PCIe®) 5.0 physical layer running at 32 GT/s with x16, x8 and x4 link widths. Degraded modes run at 16 GT/s and 8 GT/s with x2 and x1 link widths.
CXL interconnect adds coherency and memory semantics, thus allowing for its application in heterogeneous processing systems with a variety of host processors, memory subsystems and peripheral devices interconnected. CXL has applications in standard computer systems, Artificial Intelligence, Machine Learning, communication systems, and High Performance Computing. Emerging applications require a diverse mix of CPUs, GPUs, FPGAs, peripherals such as smart NICs, and other accelerators interconnected via an open industry standard protocol with the necessary features which CXL provides. CXL provides a rich set of three protocols that include 1) CXL.io based on PCIe, 2) CXL.cache and 3) CXL.memory semantics. CXL uses the PCIe stack offering full interoperability with PCIe.
MindShare’s Fundamentals of CXL Architecture course provides an overview of platform architectures and use cases of the three CXL protocols using Type 1, Type 2 and Type 3 devices. The course then provides a board understanding of the role of the layers that make up a CXL port design: Transaction Layer, Link Layer, ARB/MUX and Flex Bus Logical and Electrical Physical Layer.
You Will Learn:
- CXL system architectures with Type 1, Type 2 and Type 3 devices
- CXL transaction protocol overview
- CXL switches overview
- CXL port design overview: Transaction, Link, ARB/MUX and Flex Bus Physical Layers
Course Length: 1-Day
US Pacific Time Zone Times:
Start time: 9:00am
End time: 5:00pm
Lunch break between noon-1:00pm
Who Should Attend?
Engineering managers and designers looking to understand basic features and capabilities of CXL.
- CXL Features and Architecture Overview
- Limitations of interconnects that do not support coherency and memory semantics
- CXL and Flex Bus Link features
- CXL.io, CXL.cache, CXL.memory
- Type 1 (devices with cache), Type 2 (devices with memory) and Type 3 (memory expander with no compute engine) devices
- Layered architecture overview
Basic understanding of serial bus architectures such as PCI Express or QuickPath Interconnect. Computer architecture fundamentals. Knowledge or Intel or AMD processor architectures.
- Students will be provided with a PDF version of the presentation materials used in class